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Hardware implementation of “Supplementary symmetrical logic circuit structure” concepts

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2 Author(s)
Olson, D. ; EDO LLC, Big Bear City, CA, USA ; Current, K.W.

A test chip was fabricated in a standard 1.2-micron CMOS technology using Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) concepts. The test chip demonstrated several ternary logical functions as well as the flexibility of the SUS-LOC structure. Logic functionality and switching performance of the chip were simulated and verified experimentally. Simulated and experimental results are presented and discussed

Published in:

Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on

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