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Standard CMOS implementation of a multiple-valued logic signed-digit adder based on negative differential-resistance devices

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4 Author(s)
A. F. Gonzalez ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; M. Bhattacharya ; S. Kulkarni ; P. Mazumder

This paper presents MOS-NDR, a new prototyping technique for multiple-valued logic circuits combining MOS transistors and multipeak negative differential-resistance (NDR) devices such as resonant-tunneling diodes (RTDs). MOS-NDR emulates the folded current-voltage characteristics of NDR devices such as RTDs using only NMOS transistors, MOS-NDR has enabled the development of a fully integrated multivalued signed-digit full adder (SDFA) circuit by means of a standard 0.6-micron CMOS process technology. The prototype has been fabricated and correct operation has been verified. The circuit dimensions are 123.75 by 38.7 microns, which is more than 15 times smaller than the area required by the equivalent hybrid RTD-CMOS prototype. The propagation delay of the hybrid RTD-CMOS design is estimated to be close to six times higher than that of the MOS-NDR implementation

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Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on

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