By Topic

Implementation of multiple-valued multiplier on GF(3m) using current mode CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hyeon Kyeong Seong ; Dept. of Comput. Sci. & Eng., Sangji Univ., South Korea ; Jai Seok Choi ; Boo Sik Shin ; Heung Soo Kim

The multiplication algorithm of two polynomials on finite fields GF(3m) is presented. The 3-valued multiplier of the serial-in/parallel-out modular structures on GF(33) to be performed on the presented multiplication algorithm is implemented by current-mode CMOS. The current-mode CMOS 3-valued multiplier is implemented two GF(3) multipliers and two GF(3) adders. Performances of the proposed circuits are evaluated using Pspice simulations with 2.0 μm standard CMOS device parameters, 20 μA unit current level and 3.3 V VDD voltage supply

Published in:

Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on

Date of Conference:

2000