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A 0.13 μm poly-SiGe gate CMOS technology for low-voltage mixed-signal applications

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4 Author(s)
Y. V. Ponomarev ; Philips Res. Lab., Eindhoven, Netherlands ; P. A. Stolk ; C. J. J. Dachs ; A. H. Montree

We present here a novel approach to CMOS fabrication based on advanced lateral channel doping profiling technique coupled to gate workfunction engineering. The performance of this technology for both digital and analog applications is evaluated in detail to illustrate that it satisfies the requirements for mixed digital-analog circuitry. The use of asymmetric source/drain lateral profiles proves to be especially beneficial to analog applications

Published in:

IEEE Transactions on Electron Devices  (Volume:47 ,  Issue: 7 )