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A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS

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2 Author(s)
N. Krishnapura ; Columbia Univ., New York, NY, USA ; P. R. Kinget

A 5.3-GHz low-voltage CMOS frequency divider whose modulus can be varied from 220 to 224 is presented. Programmability is achieved by switching between different output phases of a D-flip-flop (DFF). An improved glitch-free phase switching architecture through the use of retimed multiplexer control signals is introduced. A high-speed low-voltage DFF circuit is given. The programmable divider fabricated in 0.25-/spl mu/m technology occupies 0.09 mm/sup 2/; it consumes 17.4 mA at 1.8 V and 26.8 mA at 2.2 V. Operation of 5.5 GHz with 300-mV/sub pk/ single-ended input is achieved with a 2.2-V supply. The residual phase noise at the output is -131 dBc/Hz at an offset of 1 kHz from the carrier while operating from a 5.5 GHz input.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:35 ,  Issue: 7 )