Referenced Items are not available for this document.
A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective production capability due to the lesser number of processing steps. By using this process technique, a remarkably increased high density (100 Mcell/inch/sup 2/) trench gate power MOSFET with a cell pitch of 2.5 /spl mu/m could be effectively realized. The fabricated device had a low specific on-resistance of 1.1 m/spl Omega/-cm/sup 2/ with a breakdown voltage of -36 V.
Published in:
Electron Device Letters, IEEE
(Volume:21
,
Issue:
7
)
Date of Publication: July 2000
- Page(s):
- 365 - 367
- ISSN :
- 0741-3106
- INSPEC Accession Number:
- 6647084
- Digital Object Identifier :
- 10.1109/55.847382
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- July 2000
- Sponsored by :
- IEEE Electron Devices Society
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