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High temperature formed SiGe p-MOSFETs with good device characteristics

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2 Author(s)
Wu, Y.H. ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chin, Albert

We have used a simple process to fabricate Si/sub 0.3/Ge/sub 0.7//Si p-MOSFETs. The Si/sub 0.3/Ge/sub 0.7/ is formed using deposited Ge followed by 950/spl deg/C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. A hole mobility of 250 cm/sup 2//Vs is obtained from the Si/sub 0.3/Ge/sub 0.7/ p-MOSFET that is /spl sim/two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 /spl Aring/ Si/sub 0.3/Ge/sub 0.7/ thermal oxide grown at 1000/spl deg/C has a high breakdown field of 15 MV/cm, low interface trap density (D/sub it/) of 1.5/spl times/10/sup 11/ eV/sup -1/ cm/sup -2/, and low oxide charge of 7.2/spl times/10/sup 10/ cm/sup -2/. The source-drain junction leakage after implantation and 950/spl deg/C RTA is also comparable with the Si counterpart.

Published in:

Electron Device Letters, IEEE  (Volume:21 ,  Issue: 7 )

Date of Publication:

July 2000

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