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SuperCSPTM

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1 Author(s)
Kawahara, T. ; Fujitsu Labs. Ltd., Kawasaki, Japan

SuperCSP is fabricated by building up the interposer with high reliability encapsulant on the chip by wafer level packaging technology. New encapsulation technology enables real chip-sized package from a package perspective. It is also a known good encapsulated die (KGED) from a die perspective. The reasons why board level reliability of SuperCSP is good regardless of extremely low bump-standoff height are as follows. (1) The C.T.E of encapsulant for SuperCSP is close to that of motherboard, so that the encapsulant layer effectively reduces stress occurring in the solder interconnecting portion. (2) Encapsulant with high adhesive strength reinforces and fixes the delicate connecting portion of chip and post, and also does not allow its deformation. (3) Connecting portion of solder ball and post has a strong structure and can tolerate the stress because solder balls catch hold of the whole surface of metal posts, which stick out from the encapsulant and have a mound like structure

Published in:

Advanced Packaging, IEEE Transactions on  (Volume:23 ,  Issue: 2 )

Date of Publication:

May 2000

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