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The authors propose a novel design, called the adaptive data prefetcher, which is composed of two sectors: one is the data pool (DP), and the other is the instruction recognizer (IR). The adaptive data prefetcher can solve the data access latency problem. The instruction recognizer can decide where the needed data of the new instruction comes from. We measure and evaluate our design using SPEC CPU95. The results show that the enhanced processor architecture can be an attractive solution for CPI improvement. Such a design provides improved bus traffic, allowing room for the data prefetching buffer to be used for data prefetching.