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Using switch directories to speed up cache-to-cache transfers in CC-NUMA multiprocessors

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3 Author(s)
Iyer, R. ; Server Archit. Lab., Intel Corp., Beaverton, OR, USA ; Bhuyan, L.N. ; Nanda, A.

In this paper we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implement small fast directory caches in crossbar switches of the inter-connect medium to capture and store ownership information as the data flows from the memory module to the requesting processor. Using the stored information, the switch directory re-routes subsequent requests to dirty blocks directly to the owner cache, thus reducing the latency for home node processing such as slow DRAM directory access and coherence controller occupancies. The design and implementation details of a DiRectory Embedded Switch ARchitecture; DRESAR, are presented. We explore the performance benefits of switch directories by modeling DRESAR in a detailed execution driven simulator. Our results show that the switch directories can improve performance by up to 60% reduction in home node cache-to-cache transfers for several scientific applications and commercial workloads

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Parallel and Distributed Processing Symposium, 2000. IPDPS 2000. Proceedings. 14th International

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