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Caching single-assignment structures to build a robust fine-grain multi-threading system

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4 Author(s)
Wen-Yen Lin ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; Gaudiot, J.-L. ; Amaral, J.N. ; Gao, G.R.

We present the design, implementation, and evaluation of single assignment data structures and of a software controlled cache in an existing multi-threaded architecture platform-the Efficient Architecture for Running Threads (EARTH). The software-controlled cache (ISSC) exploits temporal and spatial locality of EARTH split-phased memory transactions for single-assignment memory references. Our experimental evaluation indicates that the caching mechanism for single-assignment storage makes the EARTH memory system more robust to variations in the latency of memory operations. As a consequence the system can be ported to a wider range of machine platforms and deliver speedup for both regular and irregular application

Published in:

Parallel and Distributed Processing Symposium, 2000. IPDPS 2000. Proceedings. 14th International

Date of Conference:

2000