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This paper presents low-power design techniques at the architectural level for design of decimation filters in a digital IF receiver for wide-area wireless data networks. A multimode decimation filter design implementing both Mobitex and Ardis networks is described. The power is reduced by a factor of 1422 and the area reduced by a factor of 7.85 compared to an optimized single-mode two-stage design. A new multistage decimation filter design tool is also presented, which compares alternative architectures on figures of merit which the low-power designer can map into technology-dependent area and power costs.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:8 , Issue: 3 )
Date of Publication: June 2000