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Memory modeling for system synthesis

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2 Author(s)
S. L. Coumeri ; Compaq Comput. Corp., Shrewsbury, MA, USA ; D. E. Thomas

We present our methodology for developing models of on-chip SRAM memory organizations. The models were created to enable the quick evaluation of energy, area, and performance of different memory configurations considered during synthesis. The models are defined in terms of parameters, such as size and mode of operation, which are known at synthesis time. Our methodology does not require knowledge of the underlying memory circuitry and provides models with average percentage errors within 8%. We examine the importance of the different parameters in the models to reduce the time required to develop the models. We found that only ten different memories from a large span of possible memory sizes are needed to obtain reasonably accurate models, with average errors within 15%. In this paper, we present our modeling methodology, discuss the important aspects in developing the models, and examine the parameters necessary in creating accurate models quickly and easily.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:8 ,  Issue: 3 )