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Verification of portable intellectual property blocks for FPGAs

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2 Author(s)
Kelly, M.E. ; Dept. of Electr. & Comput. Eng., Tennessee Univ., Knoxville, TN, USA ; Bouldin, D.W.

In the world of digital electronics, the use of intellectual property (IP) is becoming increasingly more popular in the design of field-programmable gate arrays (FPGAs). Reuse of IP cuts down on the time-to-market for a product and the overall cost for producing that product. Verified IP blocks can also serve as examples, which speed up the learning curve for a beginning engineer because a learn-by-example format is generally easier to comprehend. This paper presents several methods for synthesizing a design, and then places and routes the design with several commercially available tool suites and in the process to presents scripting methods for automating the process

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Southeastcon 2000. Proceedings of the IEEE

Date of Conference: