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Improved sense-amplifier-based flip-flop: design and measurements

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6 Author(s)
Nikolic, B. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Oklobdzija, Vojin G. ; Stojanovic, V. ; Wenyan Jia
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Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output stage latch topology that significantly reduces delay and improves driving capability. The performance of this flip-flop is verified by measurements on a test chip implemented in 0.18 /spl mu/m effective channel length CMOS. Demonstrated speed places it among the fastest flip-flops used in the state-of-the-art processors. Measurement techniques employed in this work as well as the measurement set-up are discussed in this paper.

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Solid-State Circuits, IEEE Journal of  (Volume:35 ,  Issue: 6 )