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An all-digital low-power IF GPS synchronizer

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3 Author(s)
Won Namgoong ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; Reader, S. ; Meng, T.H.

An all-digital intermediate frequency (IF) Global Positioning System (GPS) synchronizer for employment in portable electronic applications is presented. The chip performs code and carrier synchronization, decodes received data, and provides pseudorange estimates. To reduce the average power dissipation, the whole receiver is powered down and reactivated only when it needs to update its position estimate. With a lower duty cycle, the receiver spends more time in the power-down mode and the power consumption of the whole receiver is proportionately reduced. The synchronizer is therefore designed to minimize re-acquisition time between position readings. When powered up, the synchronizer searches in parallel over a window of timing uncertainty, then employs near-optimal tracking with a variable loop gain filter. With SNR=-20 dB, phase shift rate of 1 chip/s, and user velocity of 30 m/s, the synchronizer chip dissipates under 4 mW for pseudorange estimate rms error of under 7 m.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:35 ,  Issue: 6 )