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Fabrication of twin transistors using sidewall masks for evaluating threshold voltage fluctuation

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5 Author(s)
Okuno, M. ; Fujitsu Labs. Ltd., Atsugi, Japan ; Aoyama, T. ; Nakamura, S. ; Sugino, Rinji
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We propose a twin MOSFET fabrication technique to evaluate threshold voltage (Vt) fluctuations. Twin gates have been made using SiN sidewall masks that provide exactly the same gate lengths. From the difference in Vt between the twin transistors, we can evaluate the Vt fluctuation due not to a global variations across a wafer, but due to local variations. The standard deviation of the gate length difference between the twin transistors is smaller than 0.48 nm at a gate length of 95 nm.

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Microelectronic Test Structures, 2000. ICMTS 2000. Proceedings of the 2000 International Conference on

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