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Testability alternatives exploration through functional testing

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5 Author(s)
Ferrandi, F. ; Dipt. di Elettronica e Inf., Politecnico di Milano, Italy ; Ferrara, G. ; Fornara, G. ; Fummi, F.
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The aim of this paper is to show the effectiveness of a high-level approach to testability analysis and test pattern generation, when analyzing different classes of architectures implementing the same specification. A unique test set is derived on the behavioral specification, based on a functional error model, which shows a high correlation with the single stuck-at-gate-level fault model. Such a test set is then tailored to the particular gate-level implementation by transforming it into a specific test sequence, based on the scheduling adopted by the high-level synthesis. Experimental results show that the application of such test sequences allows one to accurately evaluate the testability of the architecture in terms of gate-level fault coverage, in a fraction of the time required by a gate-level test pattern generator

Published in:

VLSI Test Symposium, 2000. Proceedings. 18th IEEE

Date of Conference:

2000