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On test set generation for efficient path delay fault diagnosis

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1 Author(s)
R. C. Tekumalla ; Intel Corp., Hillsboro, OR, USA

Path delay fault testing has been widely pursued in literature, primarily because of the need for determining the optimal speed of circuit operation. The existing techniques for path delay fault diagnosis are oriented towards determining the delay defects based on a given test set. In this paper, we propose a method for modifying a given test set such that the resultant test set is more effective in determining paths with excessive delays. The process of modifying the given test set is built upon an accurate algorithm for identifying all the single and multiple faults static sensitized by a given test set. The tests are then ordered such that it becomes faster and easier to identify paths responsible for timing failures. The modified test set results in an overall improvement in test quality and better diagnosis. The proposed approach can be used before test application for modifying the test set and improving diagnosis. Experiments are performed on the ISCAS' 89 and MCNC' 91 benchmark circuits to show the effectiveness of the proposed method for path delay fault diagnosis

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VLSI Test Symposium, 2000. Proceedings. 18th IEEE

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