By Topic

Bounding circuit delay by testing a very small subset of paths

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Sharma, M. ; Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA ; Patel, J.H.

Paths in a circuit share many lines and gates and hence, under specific assumptions, path delays are linearly related to each other. The delays of all the paths in a circuit can be expressed as a linear combination of the delays of a small subset of paths called the basis path set. In this paper we present a testing methodology and efficient algorithms to establish an upper bound (in most cases greater than the circuit clock period) on the circuit delay by testing only the paths in the basis path set. Since the size of the basis path set has been shown to be at most linear in the size of the circuit, this technique has the potential of drastically reducing the number of paths that have to be tested. Experimental results for benchmark circuits are given

Published in:

VLSI Test Symposium, 2000. Proceedings. 18th IEEE

Date of Conference: