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Design of system-on-a-chip test access architectures using integer linear programming

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1 Author(s)
K. Chakrabarty ; Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA

Test access is a major problem for system-on-a-chip (SOC) designs. Since embedded cores in an SOC are not directly accessible via chip I/Os, special access mechanisms are required to test them after system integration. An efficient test access architecture should reduce test cost and time-to-market by minimizing test application time. We address several issues related to the design of test access architectures. Even though these design problems are NP-complete, they can be solved exactly using integer linear programming (ILP). As a case study, the ILP models for two hypothetical but representative systems are solved using a public-domain ILP software package

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VLSI Test Symposium, 2000. Proceedings. 18th IEEE

Date of Conference: