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Timing analysis of combinational circuits including capacitive coupling and statistical process variation

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2 Author(s)
B. Choi ; Intel Corp., Chandler, AZ, USA ; D. M. H. Walker

Capacitive coupling between interconnects can lead to pattern-dependent delay variation. Statistical process fluctuations result in variation in gate and interconnect delays, and interconnect coupling. These effects become increasingly important in deep submicron circuits. In this work we describe a statistical timing analyzer for combinational circuits that takes these effects into account. The tool searches for input vectors that sensitize the longest path and maximizes the delay on these paths due to capacitive coupling. The best and worst-case timing on the paths is then computed using random gate delay variation and spatially-correlated interconnect parasitic variation. We demonstrate timing analysis results on a subset of the ISCAS85 circuits

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VLSI Test Symposium, 2000. Proceedings. 18th IEEE

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