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True background calibration technique for pipelined ADC

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3 Author(s)
Sonkusale, S. ; Dept. of Electr. Eng., Pennsylvania Univ., Philadelphia, PA, USA ; Van der Spiegel, J. ; Nagaraj, K.

A digital background calibration technique for a pipelined analogue-to-digital converter (ADC) is presented. The calibration technique involves the use of a slow, but accurate, ADC in conjunction with a least-mean squares (LMS) algorithm to find the parameters, which correct for residue errors such as finite opamp gain error, capacitor ratio mismatch and charge injection error in a nonideal pipeline stage, resulting in a significant improvement in the INL and the DNL of the ADC

Published in:

Electronics Letters  (Volume:36 ,  Issue: 9 )

Date of Publication:

27 Apr 2000

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