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Software performance estimation strategies in a system-level design tool

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5 Author(s)
J. R. Bammi ; Cadence Design Syst. Inc., San Jose, CA, USA ; E. Harcourt ; W. Kruitzer ; L. Lavagno
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High-level cost and performance estimation, coupled with a fast hardware/software co-simulation framework, is a key enabler to a fast embedded system design cycle. Unfortunately, the problem of deriving such estimates without a detailed implementation available is difficult. In this paper we describe two approaches to solve software cost and performance estimation problem, and how they are used in an embedded system design environment. A source-based approach uses compilation onto a virtual instruction set, and allows one to quickly obtain estimates without the need for a compiler for the target processor. An object-based approach translates the assembler generated by the target compiler to "assembler-level," functionally equivalent C. In both cases the code is annotated with timing and other execution related information (e.g., estimated memory accesses) and is used as a precise, yet fast, software simulation model. We contrast the precision and speed of these two techniques comparing them with those obtainable by a state-of-the-art cycle-based processor model.

Published in:

Hardware/Software Codesign, 2000. CODES 2000. Proceedings of the Eighth International Workshop on

Date of Conference:

5-5 May 2000