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A simple and efficient measurement method for characterizing capacitance matrix of multilayer interconnection in VLSI

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3 Author(s)
Mido, T. ; VLSI Design & Educ. Center, Tokyo Univ., Japan ; Ito, H. ; Asada, K.

A compact new test structure for direct extraction of components of the capacitance matrix for multilayer interconnections is presented. In this new method, each capacitive component in integrated structures is separately and directly obtained from measurement, and the total pads are kept to eight, independent of the size of the target matrix. As a result of evaluation of measurement errors caused by the asymmetry of structures, this new method can measure components of capacitance matrix with a precision of femto-farad order

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Semiconductor Manufacturing, IEEE Transactions on  (Volume:13 ,  Issue: 2 )