Identification of plasma-induced damage conditions in VLSI designs

Typically, the plasma charging effect is investigated by using antenna test structures that do not replicate well enough conditions occurring in real VLSI integrated circuits (ICs). Consequently, understanding, modeling, and detection of plasma-charging-induced gate oxide damage in real IC's is often inadequate. This paper discusses a new plasma-charging monitoring technique that assesses the extent of the above problem. This technique employs a multiplexed antenna monitoring (MAM) test structure with 400+ antenna configurations to determine the dependency between IC layout and the extent of gate oxide damage. The paper reports the results of application of this technique to a 0.35-/spl mu/m, 75-/spl Aring/ gate oxide, CMOS technology. The obtained results lead to a new definition of "antenna ratio" that is supposed to capture plasma-charging conditions in real VLSI circuits.