By Topic

CMOS shallow-trench-isolation to 50-nm channel widths

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
P. VanDerVoom ; Intel Corp., Portland, OR, USA ; D. Gan ; J. P. Krusius

The applicability of shallow-trench-isolation (STI) for CMOS to 50-nm channel widths has been explored. Transistors with channel width to 50 nm and trench width to 200 nm have been fabricated. A comparison of several oxide-filled and polysilicon field-plate-filled STI structures is presented including processing, device performance, and isolation leakage. It is shown that Vth roll off as a function of channel width can be made as small as 65 mV and 145 mV at 100 nm channel width for polysilicon and oxide filled STI, respectively. Off-state currents less than 5×10-12 A/μm and subthreshold slope around 80 mV/dec have been reached. Isolation breakdown voltages are about 8 V. Poly-filled STI effectively reduces channel edge effects, and provides excellent off-state, on-state, and turn-on characteristics all the way to 50-nm channel widths

Published in:

IEEE Transactions on Electron Devices  (Volume:47 ,  Issue: 6 )