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CMOS shallow-trench-isolation to 50-nm channel widths

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3 Author(s)
VanDerVoom, P. ; Intel Corp., Portland, OR, USA ; Gan, D. ; Krusius, J.P.

The applicability of shallow-trench-isolation (STI) for CMOS to 50-nm channel widths has been explored. Transistors with channel width to 50 nm and trench width to 200 nm have been fabricated. A comparison of several oxide-filled and polysilicon field-plate-filled STI structures is presented including processing, device performance, and isolation leakage. It is shown that Vth roll off as a function of channel width can be made as small as 65 mV and 145 mV at 100 nm channel width for polysilicon and oxide filled STI, respectively. Off-state currents less than 5×10-12 A/μm and subthreshold slope around 80 mV/dec have been reached. Isolation breakdown voltages are about 8 V. Poly-filled STI effectively reduces channel edge effects, and provides excellent off-state, on-state, and turn-on characteristics all the way to 50-nm channel widths

Published in:

Electron Devices, IEEE Transactions on  (Volume:47 ,  Issue: 6 )

Date of Publication:

Jun 2000

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