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A 5-GHz CMOS wireless LAN receiver front end

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3 Author(s)
Samavati, H. ; Center for Integrated Syst., Stanford Univ., CA, USA ; Rategh, H.R. ; Lee, T.H.

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-/spl mu/m CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:35 ,  Issue: 5 )