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A source-line programming scheme for low-voltage operation NAND flash memories

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4 Author(s)
K. Takeuchi ; Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan ; S. Satoh ; K. Imamiya ; K. Sakui

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 /spl mu/s/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:35 ,  Issue: 5 )