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For realizing HgCdTe focal plane arrays on alternate substrates (Si or GaAs), CdTe buffer layers are essential. Bulk CdTe/CdZnTe substrates are also used for LPE growth of HgCdTe. A model for the effect of the n-CdTe substrate resistivity on the quantum efficiency, /spl eta/, and the dynamic resistance-area product, R/sub d/A, of a n/sup +/-on-p HgCdTe backside illuminated photodiode has been developed, taking into account the effect of the graded heterointerface between CdTe/CdZnTe and HgCdTe on the homojunction photodiode. The issue of how low the substrate/buffer layer resistivity can be, without degrading the performance of the photodiode, has been addressed. For low substrate resistivities, the R/sub d/A can drop by about 50%, while the quantum efficiency decreases by about 5%. It has been found that as low as 2 /spl Omega/-cm for long wavelength IR photodiodes (cutoff wavelength 14 /spl mu/m) is acceptable. To obtain the R/sub d/A and /spl eta/ from the band profile, a linear approximation has been used in which the interface barrier region has a constant electric field, while the bulk of the epilayer has no electric field. General expressions have been derived for the R/sub d/A and /spl eta/ in this two-region model. Our solutions are valid for both high and low electric fields, unlike previously derived solutions in the literature valid either in the one-region low-field case or the two-region, high-field approximation.