Cart (Loading....) | Create Account
Close category search window

On redundant path delay faults in synchronous sequential circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tekumalla, R.C. ; Intel Corp., Hillsboro, OR, USA ; Menon, P.R.

A path delay fault in a sequential circuit will affect circuit timing only if it can be activated during normal operation of the circuit. Since vector pairs that can be applied to the next-state logic of a nonscan sequential circuit are restricted by the available state transitions, some faults may be impossible to activate. Such faults are redundant and need not be tested. In this paper, we present a method of identifying redundant path delay faults in the next-state logic implemented in a two-level sum of products form and extend it to multilevel realizations. Experimental results on MCNC'91 benchmarks show that large fractions of faults in most of the MCNC'91 benchmarks are redundant

Published in:

Computers, IEEE Transactions on  (Volume:49 ,  Issue: 3 )

Date of Publication:

Mar 2000

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.