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Systolic arrays-warp speed ahead for compute-bound problems using systolic arrays

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2 Author(s)
Singh, S. ; Illinois Inst. of Technol., Chicago, IL, USA ; Han, J.-Y.

The nature of parallel processing and the operation of high-speed parallel computing structures highly suited for implementation in VLSI are explained. As an example, a systolic array configuration for matrix vector multiplication is considered. Practical implementation issues that need to be resolved are discussed. These concern solving problems larger than array size, mapping of algorithms to arrays, lack of programmability, clock skew, reliability, and design for large systolic arrays.<>

Published in:

Potentials, IEEE  (Volume:10 ,  Issue: 1 )