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A new IEEE 1149.1 boundary scan design for the detection of delay defects

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2 Author(s)
Sungju Park ; Dept. of Comput. Sci. & Eng., Hanyang Univ., Ansan, South Korea ; Taehyung Kim

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores cannot be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects by postponing the UpdateDR with EXTEST instruction. Furthermore, 2log(N+2) interconnect test patterns are proposed for both static and delay testing

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Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings

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