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Virtual fault simulation of distributed IP-based designs

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4 Author(s)
M. Dalpasso ; Dipt. di Elettronica e Inf., Padova Univ., Italy ; A. Bogliolo ; L. Benini ; M. Favalli

Fault simulation and testability analysis are major concerns in design flows employing intellectual-property (IP) protected virtual components. In this paper we propose a paradigm for the fault simulation of IP-based designs that enables testability analysis without requiring IP disclosure, implemented within the JavaCAD framework for distributed design. As a proof of concept, stuck-at fault simulation has been performed for combinational circuits containing virtual components

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Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings

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