Referenced Items are not available for this document.
Fault simulation and testability analysis are major concerns in design flows employing intellectual-property (IP) protected virtual components. In this paper we propose a paradigm for the fault simulation of IP-based designs that enables testability analysis without requiring IP disclosure, implemented within the JavaCAD framework for distributed design. As a proof of concept, stuck-at fault simulation has been performed for combinational circuits containing virtual components
Published in:
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Date of Conference: 2000
- Page(s):
- 99 - 103
- Meeting Date :
- 27 Mar 2000-30 Mar 2000
- Print ISBN:
- 0-7695-0537-6
- INSPEC Accession Number:
- 6622464
- Conference Location :
- Paris
- Digital Object Identifier :
- 10.1109/DATE.2000.840023
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