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1.2-V CMOS op-amp with a dynamically biased output stage

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3 Author(s)
Giustolisi, G. ; Dipt. Elettrico, Elettronico e Sistemistico, Catania Univ., Italy ; Palmisano, G. ; Segreto, T.

A very low-voltage operational amplifier in a standard CMOS process with a 0.75 V threshold voltage is presented. It uses a novel dynamically biased output stage based on the switched-capacitor approach. Thanks to this, drive performance is greatly improved and accurate current control is also achieved. The amplifier is capable of working with a power supply as low as 1.2 V while providing a -74 dB total harmonic distortion with a 700 mV peak-to-peak output voltage into a 500 /spl Omega/ and 20 pF output load. The open-loop gain and the gain-bandwidth product are higher than 90 dB and 2.2 MHz, respectively.

Published in:
Solid-State Circuits, IEEE Journal of  (Volume:35 ,  Issue: 4 )

Date of Publication: April 2000

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