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Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-/spl mu/m silicide CMOS process

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2 Author(s)
Ming-Dou Ker ; Integrated Circuits & Syst. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Wen-Yu Lo

A new design of the diode string with very low leakage current is proposed for use in the ESD clamp circuits across the power rails. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the leakage current of this new diode string with six stacked diodes at 5 V (3.3 V) forward bias can be reduced to only 2.1 (1.07) nA at a temperature of 125/spl deg/C in a 0.35 /spl mu/m silicide CMOS process, whereas the previous designs have a leakage current in the order of mA. The total blocking voltage of this new design with NCLSCR can be linearly adjusted by changing the number of the stacked diodes in the diode string without causing latch-up danger across the power rails. From the experimental results, the human-body-model ESD level of the ESD clamp circuit with the proposed low-leakage diode string is greater than 8 kV in a 0.35 /spl mu/m silicide CMOS process by using neither ESD implantation nor the silicide-blocking process modifications.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:35 ,  Issue: 4 )