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We present design considerations for programmable high-frequency continuous-time filters implemented in standard digital CMOS processes. To reduce area, accumulation MOS capacitors are used as integrating elements. The filter design problem is examined from the viewpoint of programmability. To allow frequency scalability without deterioration of noise performance and of the frequency response shape, we employ a technique called "constant-capacitance scaling," which assures that even parasitic capacitances remain invariant when transconductors are switched in and out of the filter. This technique is applied to the design of a programmable fourth order Butterworth continuous-time filter with a bandwidth programmable from 60 to 350 MHz implemented in a 0.25-/spl mu/m digital CMOS process. The filter has a dynamic range of 54 dB, dissipates 70 mW from a 3.3-V supply, and occupies an area of 0.15 mm/sup 2/.
Date of Publication: April 2000