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A 450 MHz 64 b RISC processor using multiple threshold voltage CMOS

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18 Author(s)
Yamashita, T. ; Device Dev. Center, Hitachi Ltd., Tokyo, Japan ; Yoshida, N. ; Sakamoto, M. ; Matsumoto, T.
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A 450 MHz 64 b RISC processor die contains 8.3 M logic-gate transistors and 20 M RAM transistors. 0.25 /spl mu/m CMOS with 0.2 /spl mu/m Lg, 4 nm tox, 1.8 V Vdd, and 7-layer metal technology is used. Multiple-threshold-voltage design with minimum standby current is introduced. Previously-reported application of this technique is to limited to static circuits. Here it is applied not only to static circuits, but also to clock-distribution drivers, register files and dynamic circuits in RAM macros. Precise clock-skew control, PLL jitter minimization, and optimized buffer insertion on long wires are carried out in accordance with the critical path analysis.

Published in:

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Date of Conference:

9-9 Feb. 2000