By Topic

UltraSPARC-III: a 3rd generation 64 b SPARC microprocessor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

20 Author(s)
Lauterbach, G. ; Sun Microsyst., Palo Alto, CA, USA ; Greenley, D. ; Ahmed, S. ; Boffey, M.
more authors

UltraSPARC-III (US-III) is a 64 b 800 MHz 4-instruction-issue superscalar microprocessor for high-performance desktop workstation, work group server, and enterprise server platforms. On-chip caches include a 64 kB 4-way associative for data, 32 kB 4-way associative for instructions, a 2 k B 4-way associative data prefetch cache, and a 2 kB 4-way associative write. A 90 kB on-chip tag array supports the off-chip 8 MB unified second-level cache. The 23 M-transistor chip in a 0.15 /spl mu/m, 7-layer metal process consumes 60 W from a 1.5 V supply.

Published in:

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Date of Conference:

9-9 Feb. 2000