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Modern high-speed systems operate at more than hundreds of MHz clock frequency using clock skew compensation techniques and source synchronization. In these high-speed systems, the jitter and phase difference of the DLL or PLL are critical in determining system operating frequency. The phase-locked loop (PLL) and delay-locked loop (DLL) are widely used to eliminate the clock skew in synchronous DRAM, Rambus DRAM, serial-link and high-speed interface applications. However, it is difficult to obtain both low jitter and adequate lock-on time using conventional DLL and PLL architectures because the analog DLL and PLL can generate a low-jitter clock signal with a narrow loop bandwidth at the expense of long lock-on time. The DLL and PLL still have non-negligible phase difference between reference and internal clocks. The phase difference comes from the mismatch between the charge and discharge current caused by V/sub DS/ difference in Charge Pump (CP) when the loop is locked. As an alternative, many open loop delay-line clock synchronization circuits such as SMD and RDL are used for SDRAM application because of lock-on in only 2 clock cycles. However, their phase difference (maximum phase difference=unit delay of delay line) is relatively large compared to that of the PLL or DLL.