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This paper describes a 16 b clock-powered microprocessor that dissipates only 2.9 mW at 15.8 MHz from laboratory measurements. Clock-powered logic (CPL) has been developed as a new approach for designing and building low-power VLSI systems. In CPL, the clock signals serve as a source of ac power for the large on-chip capacitive loads. By exploiting adiabatic charging and an energy conserving clock driver, it is possible to build ultra-low-power CMOS processors with this approach. Previously, a CPL processor was demonstrated in a 0.5 /spl mu/m n-well CMOS process. Laboratory measurements confirmed that it was possible and practical to recover and reuse large amounts (upwards of 80%) of the on-chip capacitive energy for a 16 b pipelined general-purpose CMOS processor. The measurements and simulation data analysis also pointed out some of the shortcomings of the original design approach which limited the speed, voltage scalability, and robustness of the processor.
Date of Conference: 9-9 Feb. 2000