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The microprocessor system in portable electronic devices often has a time-varying computational load which is comprised of: (1) compute-intensive and low-latency processes, (2) background and high-latency processes, and (3) system idle. The key design objectives for the processor systems in these applications are providing the highest possible peak performance for the compute-intensive code (e.g., handwriting recognition, image decompression) while maximizing the battery life for the remaining low performance periods. If clock frequency and supply voltage are dynamically varied in response to computational load demands, then energy consumed per process can be reduced for the low computational periods, while retaining peak performance when required. This strategy, which achieves the highest possible energy efficiency for time-varying computational loads, is called dynamic voltage scaling (DVS).
Date of Conference: 9-9 Feb. 2000