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The ever increasing demand for denser flash memories leads to the multilevel (ML) storage approach, where any memory cell is programmed to one of m=2/sup n/ predetermined states and can hence store n bits. This 64 Mb 4-level cell (2b/cell) flash memory device uses a triple-metal triple-well p-bulk 0.18 /spl mu/m CMOS process featuring shallow trench isolation (STI) for denser memory array packing. The device (programming channel hot electron injection, erasing Fowler-Nordheim tunneling) is organized in 64 identical sectors (512 rows by 1024 columns) with a NOR architecture. Data input/output (I/O) can be selected (16 or 32). A dedicated pad supplies the I/O buffers to allow direct interfacing to external low voltage (i.e., 1.8 V) devices, as is required in most portable applications. The pull-up p-channel transistor in the output buffer is driven with a negative-bootstrapped voltage to provide adequate drive capability at low supply voltage (switching time is 10 ns with a 50 pF load at 1.8 V). All high voltages needed for memory operation (programming, erasing, and reading) are generated on-chip by charge-pump voltage multipliers, starting from the single 3 V supply. Reading can be both in asynchronous mode (130 ns access time) and in burst mode. For the latter, continuous and pipeline modes are provided, with up to 50 MHz data rate and different data output latency and burst size. Both sequential and interleaved data output is available. To achieve sufficiently tight threshold voltage distributions, stair-case-gate voltage programming and program and verify techniques are used.