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The digital display interface for an ultra-high resolution flat panel (3200/spl times/2400-pixels) requires 16 Gb/s bandwidth; moreover, 20 Gb/s is required when using an 8B10B encoder to increase serial data transmission accuracy. Low power consumption and low cost are also essential for consumer applications. These requirements are supported by multi-channel transmission, such as four 5 Gb/s CMOS LSIs, which is an effective approach to achieving an aggregate bandwidth of 20 Gb/s. There are two system problems in developing a multi-channel transmitter (TX) and receiver (RX) LSIs. One is the phase difference between multiple chips due to the data skew caused by differences between transmission cable lengths. The other is the frequency difference between the TX and RX system clocks. In response to these problems, we have developed compensation technology featuring the use of an elastic buffer for both the phase and frequency differences. Moreover, to achieve 6 Gb/s operation, a self-alignment phase detector with parallel output for a high-speed clock and data recovery circuit (CDR) and a 500 MHz fully pipelined 8B10B encoder are developed.