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High-speed frequency dividers, as typically needed in optical and satellite communication systems, are often used as showcases for new high-speed technologies. The development in broadband networks such as the 10 Gb/s ethernet, however, has raised the question of whether it is possible to realize the required circuits including these most demanding ones in a low-cost mainstream digital CMOS process. Recent studies suggest that it is difficult to design, in standard 0.25 /spl mu/m digital CMOS and using known circuit topologies, a 1.8 V static 1/2 frequency divider for operation beyond 5 GHz. The work described here demonstrates a circuit topology which overcomes a problem in high-speed divider designs and, therefore, can be used to design such a divider for input frequencies up to 10 GHz and beyond with relative ease.