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A 1 GHz Alpha microprocessor

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19 Author(s)
B. J. Benschneider ; Compaq Comput. Corp., Shrewsbury, MA, USA ; Sungho Park ; R. Allmon ; W. Anderson
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A 6-way out-of-order issue custom VLSI implementation of the Alpha architecture runs at >1 GHz. The 13.1/spl times/14.7 mm/sup 2/ die contains 15.2 M transistors and utilizes 0.18 /spl mu/m CMOS which includes 7 aluminum interconnect layers and flip-chip packaging. The design of this chip is highly leveraged from an existing 0.35 /spl mu/m, 6-way issue, 6 metal layer implementation with wire-bond packaging technology. The chip contains two on-chip cache arrays; a 64 kB 2-way set associative instruction cache and 64 kB 2-way set associative dual-ported data cache.

Published in:

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Date of Conference:

9-9 Feb. 2000