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A 3.3 V, 12b, 50MSample/s A/D converter in 0.6 /spl mu/m CMOS with over 80 dB SFDR

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6 Author(s)
Hui Pan ; Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA ; Segami, M. ; Choi, M. ; Jing Cao
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Modern wireless base stations digitize the entire received frequency band, and separate individual channels with digital filters. This requires an A/D converter (ADC) with an effective resolution bandwidth of 20 MHz or more, and a spurious-free dynamic range (SFDR) greater than 85 dB to avoid confusion of a weak received channel with spurious tones. To date, only bipolar ADCs have met these specifications. This high-SFDR wideband ADC implemented in 0.6 /spl mu/m CMOS on a 3M1P epi substrate requires no trimming, calibration or dithering.

Published in:

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Date of Conference:

9-9 Feb. 2000

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