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Return-limited inductances: a practical approach to on-chip inductance extraction

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2 Author(s)
K. L. Shepard ; Dept. of Electr. Eng., Columbia Univ., New York, NY, USA ; Zhong Tian

Decreasing slew rates and efforts to reduce the resistance-capacitance (RC) delays of on-chip interconnect through design and technology have resulted in the growing importance of inductance in analyzing interconnect response for timing and noise analysis. In this paper, we consider a practical approach for extracting approximate inductances of on-chip interconnect. This approach, which we call the method of return-limited inductances, is based on performing the inductance modeling of signal lines and power-ground lines independently and on taking advantage of the power and ground distribution of the chip to localize inductive coupling. A set of simple geometry-based matrix decomposition rules guide sparsification in these extractions

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:19 ,  Issue: 4 )