By Topic

Compiler/hardware co-design for instruction boosting in ILP processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Wang, L. ; Dept. of Inf. Eng., Feng Chia Univ., Taichung, Taiwan ; Yang, T.C.

One of the most important issues in instruction-level parallelism (ILP) processors involves the boosting of instructions across conditional branches for speculative execution. A compiler scheduling technique named LESS with a renaming function is proposed for the elimination of hazards that incorrectly overwrite a value when the branch is incorrectly predicted during speculative execution. The hardware implementation for this method is relatively simple and rather efficient. Simulation results show that the speedups achieved by LESS art better than other existing methods. For example, under the superscalar execution model, with an issue rate of 8, the average performance improvement by LESS can be expected to be 13% better than that of the CRF scheme, a solution reported recently with a scheduling skeleton similar to LESS

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:146 ,  Issue: 6 )