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Mapping matrix multiplication algorithm onto optimal fault-tolerant systolic array

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5 Author(s)
Milovanovic, I.Z. ; Fac. of Electron. Eng., Nis Univ., Serbia ; Tokic, T.I. ; Stojcev, M.K. ; Milovanovic, E.I.
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An approach to the design of fault-tolerant hexagonal systolic array (SA) for matrix multiplication is described. The approach comprises of three steps. First, redundancies are introduced at the computational level by deriving three equivalent algorithms but with disjoint index spaces. Second, we perform the accommodation of index spaces to the projection direction to obtain a hexagonal SA with an optimal number of processing elements (PE) for a given problem size. Finally, we perform mapping of the accommodated index spaces using a valid transformation matrix. As a result we obtain an SA with an optimal number of PEs which perform fault-tolerant matrix multiplication. In the case of square matrices of order N×N this array comprises N2 +2N PEs

Published in:

Microelectronics, 2000. Proceedings. 2000 22nd International Conference on  (Volume:2 )

Date of Conference:

2000