By Topic

Mapping matrix multiplication algorithm onto optimal fault-tolerant systolic array

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
I. Z. Milovanovic ; Fac. of Electron. Eng., Nis Univ., Serbia ; T. I. Tokic ; M. K. Stojcev ; E. I. Milovanovic
more authors

An approach to the design of fault-tolerant hexagonal systolic array (SA) for matrix multiplication is described. The approach comprises of three steps. First, redundancies are introduced at the computational level by deriving three equivalent algorithms but with disjoint index spaces. Second, we perform the accommodation of index spaces to the projection direction to obtain a hexagonal SA with an optimal number of processing elements (PE) for a given problem size. Finally, we perform mapping of the accommodated index spaces using a valid transformation matrix. As a result we obtain an SA with an optimal number of PEs which perform fault-tolerant matrix multiplication. In the case of square matrices of order N×N this array comprises N2 +2N PEs

Published in:

Microelectronics, 2000. Proceedings. 2000 22nd International Conference on  (Volume:2 )

Date of Conference: